Massdriver Posted August 17, 2020 Share Posted August 17, 2020 Quote Based on our exclusive report and from what Intel has talked about in regards to its Ponte Vecchio chip, it looks like Intel is all onboard the MCM train with each chip consisting of several Xe GPU tiles that will be interconnected together to form a monster of a GPU. Here are the actual EU counts of Intel's various MCM-based Xe HP GPUs along with estimated core counts and TFLOPs (You can read more about these impressive performance figures which were presented by Intel over here) : Xe HP (12.5) 1-Tile GPU: 512 EU [Est: 4096 Cores, 10.6 TFLOPs 1.3 GHz, 150W] Xe HP (12.5) 2-Tile GPU: 1024 EUs [Est: 8192 Cores, 21.2 1.3 GHz, TFLOPs, 300W] Xe HP (12.5) 4-Tile GPU: 2048 EUs [Est: 16,384 Cores, 42.3 TFLOPs 1.3 GHz, 400W/500W] https://wccftech.com/intel-xe-hpg-gaming-gpus-tsmcs-6nm-process-node/ I also noticed recently that RDNA 3 (Navi 3) from AMD is rumored to be a chiplet design. Remember this has never been done before with gaming GPUs because windows can't see more than one GPU as a single GPU and we know how bad SLI and crossfire suck. Has that changed or am I misunderstanding what they're talking about? Quote Link to comment Share on other sites More sharing options...
Mr.Vic20 Posted August 17, 2020 Share Posted August 17, 2020 1 hour ago, Massdriver said: https://wccftech.com/intel-xe-hpg-gaming-gpus-tsmcs-6nm-process-node/ I also noticed recently that RDNA 3 (Navi 3) from AMD is rumored to be a chiplet design. Remember this has never been done before with gaming GPUs because windows can't see more than one GPU as a single GPU and we know how bad SLI and crossfire suck. Has that changed or am I misunderstanding what they're talking about? So far that issue has not changed, so I too am VERY interested to see how they will overcome this historic stumbling block. Quote Link to comment Share on other sites More sharing options...
Brian Posted August 17, 2020 Share Posted August 17, 2020 Quote Link to comment Share on other sites More sharing options...
cusideabelincoln Posted August 17, 2020 Share Posted August 17, 2020 Looks like the Xe HP lineup will be for datacenters only. The Xe HPG (gaming) cards will only be one chiplet (tile). As for RDNA3, having read absolutely nothing about it, they must have a some silicon for load balancing, so that Windows will only need to see one GPU. Quote Link to comment Share on other sites More sharing options...
Massdriver Posted August 18, 2020 Author Share Posted August 18, 2020 1 hour ago, cusideabelincoln said: Looks like the Xe HP lineup will be for datacenters only. The Xe HPG (gaming) cards will only be one chiplet (tile). As for RDNA3, having read absolutely nothing about it, they must have a some silicon for load balancing, so that Windows will only need to see one GPU. You're right. I should have read the article a bit better. Quote The Xe-HPG GPU is expected to use a single tile and assuming that a single tile consists of 512 EUs, we are looking at up to 4096 cores on the flagship chip. That's disappointing. I bet the RDNA 3 chip they're referring to is for datacenters as well. Quote Link to comment Share on other sites More sharing options...
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